1. Field of the Invention
This invention relates to circuits for driving a data line with a data signal, and more particularly to circuits for driving a data line with information retrieved from a memory array.
2. Description of the Prior Art
Typical memory circuits include an array of memory cells which are coupled to bit lines. The memory cells exhibit high output impedance and small output voltage swings, and the bit lines are capacitive. The bit lines are selectively coupled to amplification circuitry which drives an output pin in response to the signal on the bit lines. Of importance, it is desirable that the amplification circuitry exhibit low power dissipation and a fast response time. Unfortunately, in the past, it has been difficult to simultaneously attain both low power dissipation and a fast response time.
FIG. 1 illustrates a prior art circuit 8 for driving an output lead 20 of a memory device. Referring to FIG. 1, a bit line 10 and reference line 12 are coupled to at least one memory cell (not shown) within an array of memory cells. Bit line 10 and reference line 12 are also coupled to a sense amplifier 14 which generates therefrom an output signal SA.sub.OUT on an output lead 16. Output lead 16 is coupled to an inverter 18 which in turn drives output lead 20 with a signal INV.sub.OUT. The timing for the signals provided by circuit 8 is illustrated in FIG. 2. Referring to FIG. 2, at a time T1, data from the memory device is read, thereby causing the signal BL on bit line 10 to go low if the memory cell stores a "0". (The present description is directed toward the case in which bit line 10 is originally charged to a high voltage, i.e. bit line 10 is originally coupled to a cell which stores a 1, and is then coupled to a memory cell which stores a 0 at time T1. It is understood, however, that circuit operation would be similar if the voltage at bit line 10 was originally low and then bit line 10 was coupled to a memory cell which stored a 1.)
Output lead 16 is capacitive and sense amplifier 14 exhibits a high output impedance. Therefore output signal SA.sub.OUT from sense amplifier 14 changes slowly after time T1. Of importance, as soon as signal SA.sub.OUT crosses a voltage trigger point 22, output signal INV.sub.OUT generated by inverter 18 rises rapidly. (Inverter 18 is provided, in part, to permit the memory device to provide a steady state output signal on lead 20 without waiting for signal SA.sub.OUT to fall to ground.)
As mentioned above, it is desirable to reduce the delay between the time a memory cell is connected to sense amplifier 14 and the time valid output data is provided. In order to reduce the delay between time T1 and the time inverter 18 provides valid output data on lead 20, it is known to couple a transfer gate 30 across the input and output leads of inverter 18 as illustrated in FIG. 3. To understand how this structure works, reference is made to the timing diagram of FIG. 4. During an initial time period T2, signal INVR is inactive, transfer gate 30 is open, sense amplifier 14 receives bit line output signal BL from a first memory cell (which stores a 1) and provides signal SA.sub.OUT in response thereto. (Signal SA.sub.OUT is approximately 4 volts when reading a memory cell which stores a 1.) At the end of period T2, signal INVR goes active, transfer 30 closes, the output signal from inverter 18 is provided as the input signal to inverter 18 and therefore, the voltages at the input and output leads of inverter 18 are held at the same level, i.e., at approximately the midpoint of the voltage swing of inverter 18 (about 2.5 volts). Thereafter, the address received by the memory device changes, and at time T3, bit line 10 is connected to a second memory cell (which stores a 0), and signal BL starts to fall. However, because signal INVR is active, output lead 16 of sense amplifier 14 remains at the midpoint of the voltage swing of inverter 18. When it is desired to read the data stored in the second memory cell, signal INVR goes inactive (high) and transfer gate 30 opens (time T5). Of importance, at time T5, signal BL has fallen below voltage V.sub.ref, and output signal SA.sub.OUT from sense amplifier 14 is permitted to fall. Since the input lead of inverter 18 is at the inverter trigger point when transfer gate 30 opens, output signal SA.sub.OUT falls below the trigger point of inverter 18 almost immediately, and output signal INV.sub.OUT from inverter 18 rises rapidly. Thus, it is seen that by providing transfer gate 30 to hold the signal at lead 16 half way between ground and VCC, the delay between the time signal BL falls below voltage V.sub.ref (time T4) and the time signal SA.sub.OUT falls below trigger point 22 can be reduced. This is because it is not necessary to wait for sense amplifier 14 to discharge output lead 16 from 4 volts (the voltage on lead 16 when sense amplifier 14 senses a 1 on bit line 10, e.g. prior to time T2) to the trigger point of inverter 18 (the input lead of inverter 18 is already held at the trigger point by transfer gate 30). Thus, the delay between time T3 and the time output signal INV.sub.OUT goes high is dramatically reduced.
It is noted that signal INVR is timed to go inactive after signal BL falls at least a predetermine voltage drop V (e.g. about 100 mV) below voltage V.sub.ref. This is done to ensure that at time T5, sense amplifier 14 will start driving lead 16 with a voltage level which accurately reflects the state of the memory cell being read.
Signal INV.sub.OUT is coupled to a three-state buffer circuit 22 which drives an output lead 26. Three-state buffer circuit 22 is capable of going into a high impedance mode (also known as a three-state mode or a tri-state mode) in response to a signal OE going inactive, so that other circuitry external to the memory circuit, can drive lead 26. Circuit 22 includes a NAND gate 23, a NOR gate 24, and an output stage 25. Output stage 25 provides signal V.sub.OUT on an output lead 26 when signal OE is active (i.e. signal OE is high and signal OE is low). Three-state buffer circuit 22 goes into the three-state mode in which transistors 25a and 25b are both off when signal OE is inactive.
A structure similar to that of FIG. 3 is discussed by S. Ali et al. in "A 50-ns 256K CMOS Split-Gate EPROM", published in IEEE Journal of Solid-State Circuits in Feb., 1988, incorporated herein by reference.
As more memory cells are integrated into high density memories such as DRAMs, SRAMs, and EPROMs, it is necessary to be able to selectively drive output lead 26 with data from a larger number of bit lines. This can be done by connecting a large number of bit lines 10-1 to 10-N to a multiplexer 34, which selects one of the bit lines to drive sense amplifier 14 (FIG. 5). However, as the number of bit lines coupled to multiplexer 34 increases, so does the capacitive loading of input lead 10 of sense amplifier 14. Thus, the time required to provide valid data on input lead 10 also increases.
Another technique for integrating more bit lines onto the memory device is to provide a plurality of sense amplifiers such as sense amplifier 14 and inverters such as inverter 18 and connect each of the inverters to three-state buffer circuit 22 via a transfer gate such as transfer gate 36. (FIG. 6). Transfer gate 36 is controlled by a signal on lead 37. (In FIG. 6, blocks 38-2 to 38-N are identical to the circuitry in block 38-1). Unfortunately, if this is done, the capacitive loading on the input lead of buffer circuit 22 is increased, thus adding to the propagation delay of the output circuit. To enhance the speed with which signals are provided to buffer circuit 22, inverter 18 and the corresponding inverters in blocks 38-2 to 38-N must comprise very large transistors which provide a large switching current. Unfortunately, this also causes high power dissipation when transfer gate 30 is closed. (Of importance, inverter 18 typically comprises a P channel MOS transistor 18a and an N channel MOS transistor 18b which are both on when transfer gate 30 is closed.) Also, if the size of transistors 18a and 18b is increased, the loading on sense amplifier 14 is increased, thereby slowing the memory device. It would be desirable to reduce the power dissipation of inverter 18 and increase the speed with which data is provided on data line 20.